A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as "writes preserve values, reads ignore values," i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields.
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References
History
Mon, 20 Apr 2026 21:00:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as "writes preserve values, reads ignore values," i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields. | |
| References |
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Status: PUBLISHED
Assigner: mitre
Published:
Updated: 2026-04-20T20:30:19.577Z
Reserved: 2026-03-04T00:00:00.000Z
Link: CVE-2026-29642
No data.
Status : Received
Published: 2026-04-20T21:16:19.393
Modified: 2026-04-20T21:16:19.393
Link: CVE-2026-29642
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OpenCVE Enrichment
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Weaknesses
No weakness.